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Unit - I Multiple Microprocessor System & Buses
Unit I
Unit II
Unit III
Unit IV
Unit V
Minimum mode of 8086

The above diagram shows that Mp 8086 is connected in minimum mode.
In minimum mode different IC’s are connected with 8086 namely as 8284 clock generates IC, Buffer 74244, Latch 8282 and transceiver IC 8286 as shown in given figure.
In minimum mode of 8086 MN/MX¯¯is connected with +5v
The different memory and IO parts are connected with 8086 in minimum mode as RAM, EPROM, IO devices.
a) IC 8284:
MP does not have its own clock so we have to connect 8284 IC externally to 8086.Three pins namely CIK, RESET and READY is connected with 8086.
b) Buffer 74244:
It is used as Current Driver M/IO¯, RD¯, WR¯ and INTA¯ is connected with buffer.
c) Latch: (8282)-latch IC.
Latch IC 8282 is used to store the addresses which are always available further. ALE, BHE¯/S7 A19/S6 – A16/S3, AD15 – AD0 is connected to the i/p of latch and we get the O/P as 21-bit address i.e. A19 – A0 and BHE¯ and also AD15 – AD0 is transferred to the i/p of transceiver IC 8286.
d) 8286 Transceiver IC:
It is used as transmitting or receiving the data from memory as other I/O devices DEN¯and DT/R¯ is used to enable transceiver IC’s.
Above fig RAM, EPROM, 8259 PIC and IO devices are connected.
The Major difference between minimum mode and maximum mode is given below:

Miximum mode of 8086
Explain with suitable diagram how an 8086 MP is connected with a controller device for operation in maximum mode?

In maximum mode the different IC’s are used namely as 8288 bus controller IC, 8282 latch IC, 8284 clock generates IC, 8286 transceiver IC.
In maximum mode system of 8086 MN/MX¯ is connected with OV (logic O).
The different memory and IO devices are connected with 8086 in maximum mode as RAM, EPROM, 8259 PIC and IO devices:-
The working of IC is given below:-
1) 8284 clock generates IC’s:
Since the mp 8086 does not have its own clock, hence for clock which have to given to mp, we use 8284 IC. The ready, reset and clt pins of 8086.
2) Latch 8282:
8282 IC’s is used to store the addresses, BHE¯/S7, A19/S6 – A16/S3 and AD15 – AD0 signals are used to store the i/p of 8282 and we get the o/p as AO – A19 and BHE¯ i.e. 21 bit addresses for selecting memory and IO devices.
3) 8288 bus controller IC:
Bus Controller is used to generate different control signals because in maximum mode MP cannot generate control signal its own so for generating the different control signal we use 8288. The different control signals generated as INTA¯, IORC¯, IOWC¯, MRDC¯, MWTC¯ etc. The S2¯- S0¯ status pins are connected to the i/p of bus controller 8288.
4) Transceiver IC 8286:
Input to the 8286 is AD15 – AD0 which is connected for the latch IC and also DT/R¯ and DEN is connected to its i/p from the bus controller 8288. O/p of transceiver is D15 – D8 and D2 – D0. Data bus for high and lower bank of memory.
Internal block diagram or Architecture of 8087 (NDP)

8087 is a 40 Pin Intel IC whose internal block diagram is shown in figure.
1) Co-processor:
As 8087 cannot generate physical address (PA) of memory location, so 8087 cannot be used alone in the system. 8087 is always used along with main processor 8086/8088, so it is called Helping Processor or Co-processor.
2) Advantage of 8087:
The operation of 8087 instruction can also be performed using program of 8086 and it is called 8087 emulator. But 8087 will execute arithmetic operation nearly 100 times faster than equivalent emulator.
The interval block diagram of 8087 can be divided into two parts;
A) CONTROL UNIT (CU):
1) When power supply is made ON then 8087 CU will i/p and check BHE¯ signal and if BHE¯ i/p = 0 then it indicates that 8087 is connected with 8086. So then accordingly 8087 will adjust data bus width of 16-bits and instruction queue length of 6 bytes. If the BHE¯ input = 1 then it indicates that 8087 is connected with 8088. So accordingly 8087 will adjust data bus width of 8-bits and instruction queue length of 4 bytes.
2) Bus tracking unit in CU will i/p and check status signal S2¯, S1¯, S0¯. So 8087 will get the information about the current machine cycle and its clock cycle which main processor 8086/8088 is executing when main processor’s perform code fetch operation the CU will read instruction codes from data bus and stores them in instruction queue register (operand queue) similarly CU will read OS1 OS0 bits of main processor and accordingly it will read instruction code from register 1 of IQ.
3) CU will generate different control signal to execute memory read/memory write machine cycle as 8087 cannot generate PA. So main processor will execute first dummy read machine cycle for 8087. The CU of 8087 will i/p and store 20 bit PA and BHE¯ transferred by main processor for memory location when 8087 CU will take control of system bus from main processor then using memory address of dummy machine cycle, CU of 8087 will execute further machine cycles.
4) Status Registers: -
It will contain different error flags like stack register overflows, exponent overflow (infinity) exponent underflow (o), square root of negative number, division by zero error flag etc. It will also contain different status flags which will indicate the status of result obtained after arithmetic operation i.e. result is zero, positive, negative etc. The three bit number is status register will indicate the address of TOS of register stack.
5) Control Register’s:-
The control register in CU will cocontain different bits which are used to mark or unmark different error flags, between interrupt etc. It is also used to define the pr precision of the result i.e. in case of default 8087 will perform all internal operations in temporary real format but using control bits we can make 8087 to perform calculations using short real numbers or using long real numbers so 8087 can be made compatible with earlier smaller precision arithmetic processor. If any result is to be conver nvted from real number to integer number then control register rounding bits can be used to round off the fraction result towards +,-, zezero etc.
B) NUMERIC EXECUTION UNIT:
1) Arithmetic Module: -
All the arithmetic operations are performed in arithmetic module using arithmetic instructions like FADD, FMUL, FSQRT, and FPREM.
2) Exponent Module: -
All the calculations of exponent part are performed in exponent module.
3) Programmable Shifter: -
It is used to perform fast multiplication and division using shift operation.
4) Temporary Registers: -
It is used to share any intermediate result.
5) Microcode Control Unit: -
It will contain different logical circuits which are used to generate control signals required to execute different instructions.
6) Operand Queue: -
This is an instruction queue of 6 bytes which is used to store prefetch instructions codes.
7) Register Stack: -
NEU consists of 8 registers of 80 bits each in the form of stack. As all internal operations are performed in temporary real format, so 80 bit registers are used. When any data transfer is performed from memory to register then data is converted from Integer/BCD/Real Number into temporary real number and then stored into the register of 8087. Similarly when data is transferred back from 8087 to memory then it is converted from temporary real number into required Integer/BCD/Real Number and then stored into memory.
Data is pushed or popped from stack register in LIFO sequence. The 3 bit address of TOS is stored into status register. The TOS for different cases are shown. There is a 2 bit tag register with each stack register which will indicate status of stack register.
Block Diagram of 8089
What is I/O processor? What are its functions? Draw an internal block diagram of 8089 and explain function of each block in detail?

8089 is known as I/O processor and it is designed to work with Intel 8086 family of processor. An I/O processor is supposed to take care of all system I/O activities.
Functions: - 8089 IOP communication with host processor uses a memory table which contains details of task to be executed. These tables are prepared by host CPU to allot the task to the IOP 8089. The host interrupts IOP after allotting a task to it once IOP interrupted and reads the memory table prepared by host CPU to get the detail of allotted task. This memory table has an address of program written in 8089 instruction called as channel program 8089 executes the channel program.
Unlike 8087, the 8089 can fetch and execute its instruction on its own 8089 may be operated in tightly as loosely coupled configuration.
NOTE: In a tightly coupled configuration the 8089 shares the system bus and memory with the host CPU using its RQ¯/GTO pin.
In a loosely coupled configuration 8089 has its own local bus and communicated with the host using bus arbiter and controller.
Description of Block Diagram:-
The 8089 is divided into following functional unit.
A) CCU (Common Control Unit) :
1) All IOP operations (instructions), (DMA transfer channel attention response etc) are composed of sequences of more basic process called internal cycle.
2) A bus cycle takes one internal cycle, the execution of an instruction require several internal cycle.
3) The common control unit co ordinates the activities of IOP primarily by allocating internal cycles to various procedure units i.e. it determines which unit will execute next internal cycle.
B) ALU (Arithmetic and Logic Unit):
As usually ALU can perform unsigned binary arithmetic on 8 and 16 bit binary numbers. Arithmetic result may be up to 20 bits in length.
The available arithmetic instruction is addition, increment, and decrement. The available logical instruction are AND, OR, NOT.
C) Assembly/Disassembly Registers:
IOP 8089 allows user flexibility of data transfer between different widths buses for example 8 bit peripherals to 16 bit memory. Therefore all data entering the chip, flows through these registers and IOP uses assembly/disassembly registers when we use different width buses.
D) Instruction fetch unit:
This unit controls instruction fetching further executing channel (one at a time).
If the bus over which the instruction are being fetched is 8-bit wide the instruction are obtained on byte at a time and each fetch requires one bus cycle.
E) Bus interface unit:
The BIU runs all bus cycles, transferring instruction and data between IOP and external memory/peripherals.
BIU interact with following signals: - a)Ready b) CLH c) RQ¯/GT¯ d) S0¯-S2¯ e) LOCK¯ f) BHE¯
F) Channels:
The 8089 has two internal IO channels which can be programmed independently to handle separate IO task for the host CPU. The common ALU is shared by both the channels channel contain.
a) IO control
b) Registers 1) General Purpose A: - (GA)
2) General purpose B: - (GB)
3) General Purpose C: - (GC)
4) Tast Pointer
5) Parameter Block Pointer
6) Index (IX)
7) Byte Count (BC) 8) Mask Compare 9) Channel Control (PP) 10) PSW
General Purpose Interface Bus (GPIB) and Hewlett-Paekard interface
IEEE 488/489 BUS/General Purpose Interfacing Bus (GPIB)
It is a 24-pin standard bus which is used for connecting different I/O devices like measuring instrument, CRT, keyboard with CPU in a multiterminal system (UNIX System). The device which can be connected with the help of IEEE 488 bus can be classified into following types.
1) LISTNER :- (Output Device)
A device which can only receive data from system bus is called as listner.
Example: Printer, CRT Screen, Voltmeter etc.
2) TALKER:- (Input Device)
A device which can only transfer data to system bus is called Talker.
Example: Keyboard.
3) LISTNER AND TALKER:
A device which can receive as well as transfer data to system bus is called as Listners and Talker.
Example: Audio Cassettes, Floppy Disk, RAM Memory.
4) Controller:
A device which controls devices which are connected with system bus is called Controller. With the help of control signals the controller will specify that which device will talk and which device will listen.
Example: CPU 8086, 8088, 8085, 8089.
Using IEEE 488 bus the different devices can be connected and data transfer rate is 1MB per second.
Also GPIB has 8-bidirectional data pins this pins are used to transfer data. The GPIB has full bus management lines which functions basically as follows:-
1) IFC (Interface Clear Line):
The IFC when asserted by the controller reset all devices on the bus to a starting state. It is essentially a system reset.
2) ATN (Attention Line):
The ATN Line when asserted (low) indicates that the controller is putting a universal command on an address command such as listner on the data bus. When ATN is high, then data line contain data on status byte.
3) SRQ (Service Request):
The SRQ is similar to an interrupt. Any device that needs to transfer data on the bus asserts the SRQ line low. The controller then poles all the devices to determine which one needs services, when asserted by the system controller.
4) REN (Remote Enable Signal):
REN allows an instrument to be controlled directly by the controller rather than by its front panel switches.
5) EOI (End Of Identify Signal):
The END of identify signal is usually asserted by a talker to indicate that the transfer of block of data is completed. Finally the bus has three hand shake lines that Co-ordinates the transfer of data bytes on data bus. There are three hand shake
a) Data valid (DAV) b) Not ready for data (NRED) c) Not data accepted (NDAC)
Advantages:
The importance of GPIB is that it allows a microcomputer to be connected with several test instruments to form an integrated test system.
Direct Memory Access:
For such application such as transferring data bytes to memory from a magnetic or optical disk. However the data bytes are coming in from the disk faster than they can be read in with program instruction. In such case we use a dedicated hardware device called DMA or DMA controller to manage the data transfer.
DMA controller temporarily barrow the AB, DB and CB from MP and transfer the DB directly from DC to series of ML. because the data transfer is handled totally in hardware. It is much faster than it would be if done by program instruction. A DMA controller can also transfer data from memory to port. Some DMA devices can do memory transfer to implement fast block transfer.
The diagram given below shows how DMA controller is connected and used in an 8086 min mode. BD showing how a DMA controller operates in a microcomputer system.
DMA Operation
In a microcomputer memory and I/O device are connected together through a common system bus. The data transfer between memory and IO device can be performed by 2 methods.
A) Under MP Control:-
If data transfer between memory and IO device is performed under MP control then data is transferred through MP. This is called indirect memory access. It takes more time.
B) Under 8257 Control:-
If data is transferred between memory and IO device under control of 8257 then direct data transfer is performed between memory and IO device. This is called DMA. It takes less time 4 clock cycle/byte.
Sequence of DMA Operation:-
1) IO device will make DRQ = 1 (DMA required) in response 8257 gives HRQ = 1.
2) When MP receives HOLD i/p = 1 then MP will complete current machine cycle and enters into hold state. In hold state MP can perform any internal operation but MP will not use external add, data, control bus. In hold state MP will keep add, data control pins floating and MP HLDA = 1.
3) When 8257 receives HLDA = 1 then it will take control of system bus and start DMA operation.
4) Selection of memory location: - 8257 will transfer 16 bit address to address bus so one memory location is selected.
5) Selection of IO port: - 8257 gives DACK¯ = 0 so CS¯ = 0 hence IO device of IO port selected.
6) Data transfer from memory to O/P point. 8257 will give MEM RD¯ = 0 and IOWR¯ = 0. So 8 bit data is transferred from selected memory location to select O/P port.
7) Data transfer from I/P port to memory. 8251 gives IORD¯ = 0 and MEMWR¯ = 0 so 8 bit data is transferred from selected i/p port to selected memory location.
8) After each byte transfer the add register is increased by 1 and terminal count register TCR is decreased by 1. The same process is repeated till all data bytes are transferred between memory and IO device.
9) After completing DMA operation 8251 gives HRQ = 0 so MP will receive HOLD ip = 0 hence MP will exit from HOLD state and MP will continue its operation from machine cycle from MP has left.

What is DMA? Why DMA data transfer is faster than data transfer with program instruction explain? Describe the series of action that a DMA controller will do after it receives a request from peripheral device for data transfer? →
The DMA I/O techniques provide direct access to the memory while the MP is temporarily disabled. This allows data to be transferred between memory and the I/O device at a rate that is limited only by the speed of memory component in the system or the DMA controller. The DMA transfer speed can approach 32 to 40 MB transfer rates with today’s high speed RAM memory components.
The DMA transfer are used for many purposes but more common are DRAM, refresh, video displays for refreshing the screen and display memory system DMA transfer is also used to do high speed memory to memory transfer.
Basic DMA operation:
The two signals are used to request and acknowledge a direct memory access transfer in the MP based system. The hold pin in an input that is used to request a DMA action and the HLDA pin is an output that acknowledges the DMA action.
Whenever Hold input is placed at logic 1, a DMA action is request. The MP responds within a few clocks by suspending. The execution of pgm and by placing its address, data and control but at their high impedance state. The high impedance state causes the MP to appear as if it has been removed from its socket. This state allows external I/O devices or the other MP to gain accesses to the system buses so that memory can be accessed directly.
The HLDA output is a signal to the external requesting device that the MP has relinquished control of its memory and I/O states. The data transfer speed is determined by the speed of the memory device or a DMA controller that often control DMA transfer. If the memory speed is 100 ns (nano second) data transfer access at a rate up to 10 mb/sec. When the disk controller has the first byte of data from disk block ready it sends a DMA request DREQ signal to the DMA controller is that input of DMA controller is unmarked the DMA controller will send a hold request HRQ signal to the MP hold input. The MP will respond to this input by floating its buses and sending out a hold acknowledge signal HLDA to the DMA controller. When the DMA controller receives the HLDA signal it will send out a control signal which throws the three buses switches down to their DMA positions.
DMA controller 8257
The direct memory access or dma mode of data transfer is the fastest amongst all the modes of data transfer. In this mode, the device may transfer data directly to/from memory without any interference from the cpu.the device requests the cpu to hold its data, address and control bus,so that the device may transfer data directly to/from memory.the dma data transfer is initiated only after receiving hlda signal fom the cpu. For facilitating dma type of data transfer between several devices, a dma controller may be used.
Intel’s 8257 is a four channel dma controller designed to be interfaced with their family of microprocessors. The 8257,on behalf of the devices, requests the cpu for the bus access using local bus request input i.e hold in minimum mode.in maximum mode of the microprocessor RQ/GT Pin is used as bus request input.
INTERNAL ARCHITECTURE OF 8257:
The internal architecture of 8257 is shown in fig. the chip supports four dma channels i.e four peripherals devices can independently request for dma data transfer through these channels at a time. The dma controller has 8-bit internal data buffer a read/write unit, a control unit, a priority resolving unit along with a set of registers.
REGISTER ORGANISATION OF 8257:
The 827 performs the dma operation over four independent dma channels. Each of the four channels of 8257 has a pair of two 16-bit registers, viz dma address register and terminal count register. Also there are two common registrs for all the channels, namely mode set register and status registr. Thus there are a total of ten registers.
DMA ADDRESS REGSITER:
Each dma channels has one dma register. The function of this register is to store the address of the starting memory location,which will be accessed by the dma channel. Thus the starting address of the memory block which will be accessed by the device is first loaded in the dma address register of the channel.
TERMINAL COUNT REGISTER:
As in the previous case, each of the four dma channels of 8257 has one terminal count register(TC).this 16-bit register is used for ascertaining that the data transfer through a dma channel ceases or stops after the required number of dma cycles.
MODE SET REGISTER:
The mode set register is used for programming the 8257 as per the requirement of the system. The function of the mode set register is to enable the dma channels individually and also to set the various modes of operation.

Difference between Static and Dynamic RAM

DRAM (TMS44C256)
Fig shows an internal block diagram of TMS44C256 cmos dram. This device is a 256*4 device, so it stores 262,144 words od 4-bits each in its 20-pin package.
To read a word from a dynamic rams, a dram controller device or other circuitry asserts the write enable W¯,pin of the drams high to enable them for a read operation. It then sends the upper half of the address called the row address or page address, to the nine address inputs of the drams. The controller then asserts the row-address-strobe, RAS¯ input of the dram low to latch the row address in the dram. After the proper timing interval, the controller removes the row address and outputs the lower half of the address, called the column address, to the nine address inputs of the drams. The controller then asserts the column-address-strobe, CAS¯,inputs of the drams low to latch the column address in the drams. The timing diagram for a write cycle is nearly the same except that after it sends out the column address and CAS¯, the controller asserts the write enable W¯, Input low to enable the drams for writing, and asserts a signal which is used to gate the data written into the data inputs of the drams. To refresh a row in a dram, the row address is applied to the address inputs and the RAS¯ input is pulsed low. For this particular device each row must be refreshed at least once every 8ms. The refresh can be done in either a burst mode or in a distributed mode.
The main task you have to do to interface a bank of drams to a microprocessor:
1) multiplex the two halves of the address into each device with the appropriate RAS¯ and CAS¯ strobes.
2) provide a read/write control signal to enable data into or out of the devices.
3) refresh each row at the proper interval.
4) ensure that a read or write operation and a refresh operation do not take place at the same time.
Vme bus:
Description :
In many ways the VMEbus is equivalent or analogous to the pins of the 68000 run out onto a backplane. In many cases this could be considered a bad design. One is in theory limited to chipset buses similar to the 68000.
However, one of the key features of the 68000 was a flat 32-bit memory model, free of memory segmentation and other "anti-features". The result is that, while VME is very 68000-like, the 68000 is generic enough to make this not an issue in most cases.
Like the 68000, VME uses separate 32-bit data and address buses. The 68000 address bus was actually 24-bit and the data bus 16-bit (although it was 32/32 internally) but the designers were already looking towards a full 32-bit implementations.
In order to allow both bus widths, VME uses two different Eurocard connectors - P1 and P2. P1 contains three rows of 32 pins each, implementing the first 24 address bits, 16 data bits and all of the control signals. P2 contains one more row, which includes the remaining 8 address bits and 16 data bits.
The bus is controlled by a set of nine lines, known as the arbitration bus. All communications are controlled by the card in slot one of the Eurocard chassis, known as the arbiter module. Two arbitration modes are supported - Round Robin and Prioritized.
Regardless of the arbitration mode, a card can attempt to become the bus master by holding one of the four Bus Request lines low. With round robin arbitration, the arbiter cycles amongst Bus Request lines BR0-BR3 to determine which of the potentially-simultaneous requesters will be granted the bus. With priority arbitration, BR0-BR3 use a fixed priority scheme (BR0 lowest, up to BR3 highest) and the arbiter will grant the bus to the highest priority requestor.
When the arbiter has determined which of the bus requests to grant, it asserts the corresponding Bus Grant line (BG0 - BG3) for the level that won bus mastership. If two masters simultaneously request the bus using the same BR line, a bus grant daisy-chain effectively breaks the tie by granting the bus to the module closest to the arbiter. The master granted the bus will then indicate that the bus is in use by asserting Bus Busy (BBSY*).
At this point, the master has gained access to the bus. To write data, the card drives an address, an address modifier and data onto the bus. It then drives the address strobe line and the two data strobe lines low, to indicate the data is ready, and drives the write pin to indicate the transfer direction. There are two data strobes and an *LWORD line, so the cards can indicate if the data width is 8, 16, or 32 bits The card at the bus address reads the data and pulls the data transfer acknowledge low line when the transfer can complete. If the transfer cannot complete, it can pull the bus error line low. Reading data is essentially the same but the controlling card drives the address bus, leaves the data bus tri-stated and drives the read pin. The slave card drives read data onto the data bus and drives the data strobe pins low when the data is ready. The signalling scheme is asynchronous, meaning that the transfer is not tied to the timing of a bus clock pin
A block transfer protocol allows several bus transfers to occur with a single address cycle. In block transfer mode, the first transfer includes an address cycle and subsequent transfers require only data cycles. The slave is responsible for ensuring that these transfers use successive addresses.
Bus masters can release the bus in two ways. With Release When Done (RWD), the master releases the bus when it completes a transfer and must re-arbitrate for the bus before every subsequent transfer. With Release On Request (ROR), the master retains the bus by continuing to assert BBSY* between transfers. ROR allows the master to retain control over the bus until a Bus Clear (BCLR*) is asserted by another master that wishes to arbitrate for the bus. Thus a master which generates bursts of traffic can optimize its performance by arbitrating for the bus on only the first transfer of each burst. This decrease in transfer latency comes at the cost of somewhat higher transfer latency for other masters.
Address modifiers are used to divide the VME bus address space into several distinct sub-spaces
Bus arbitration and control:
The process of assigning control of the DTB to a requester is called arbitration.dedicated lines are reserved to co-ordinate the arbitration process among several requester.the requester is called a master and the receiving end is called the slave. Vme bus can house one to three backplane buses.two can be used as a shared bus among all processors and memory boards and the third as a local bus connecting a host processor to additional memory and i/o boards.
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