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Unit-I Architecture of 8086
Unit I
Unit II
Unit III
Unit IV
Unit V
Features of 8086 Microprocessor
• Intel 8086 was launched in 1978.
• It was the first 16-bit microprocessor.
• This microprocessor had major improvement over the execution speed of 8085.
• It is available as 40-pin Dual-Inline-Package (DIP).
• It is available in three versions:
o 8086 (5 MHz)
o 8086-2 (8 MHz)
o 8086-1 (10 MHz)
• It consists of 29,000 transistors.
The Block Diagram of 8086
The block diagram of 8086 is as shown below.
This can be subdivided into two parts namely - Bus Interface Unit and Execution Unit.
The Bus Interface Unit (BIU)
• The Bus Interface Unit consists of segment registers, adder to generate 20 bit physical address and instruction prefetch queue.
• The complete physical address which is 20 bits long is generated using 16 bit segment and offset registers using adder.
• In other words this unit is responsible for establishing communication with external devices and peripherals including memory via the bus.
• Once the physical address is sent out of BIU, the instruction and data bytes are fetched from memory and they stored into a First In First Out (FIFO) 6 byte queue.
• This Queue is 6 byte long used to store the op-codes fetched from memory in advance.
In short the function of BIU is to
• Fetch the instruction or data from memory.
• Write the data to memory.
• Write the data to the port.
• Read data from the port.
Function of Instruction Queue
1. To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory.
2. All six bytes are then held in first in first out 6 byte register called instruction queue.
3. Then all bytes have to be given to EU one by one.
4. This pre fetching operation of BIU may be in parallel with execution operation of EU, which improves the speed execution of the instruction.
Segment Registers
There are four different 64 KB segments for instructions (code), stack, data and extra data. To specify where in 1 MB of memory these 4 segments are located the processor uses four segment registers:
1. CS register: -
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register.
2. SS Register: -
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers are located in the stack segment.
3. DS register: -
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, and DX) and index register (SI, DI) is located in the data segment.
4. ES register: -
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions.
Instruction Pointer:
The Instruction Pointer or IP (also called the program counter in 8085) is a processor register that indicates where the computer is in its instruction sequence. In 8086 instruction pointer holds the address of the next instruction to be executed. In most processors, the instruction pointer is incremented automatically after fetching a program instruction, so that instructions are normally retrieved sequentially from memory, with certain instructions, such as branches, jumps and subroutine calls and returns, interrupting the sequence by placing a new value in the program counter.
Execution Unit (EU):
• The execution unit consists of registers such as 16-bit AX, BX, CX and DX and pointers like SP (Stack Pointer), BP (Base Pointer) and index registers such as SI (source index) and DI (destination index) registers.
• The 16-bit registers can be split into two 8-bit registers. For example, AX can be split into AH and AL registers.
• It has a 16 bit ALU (Arithmetic and Logical Unit), able to perform arithmetic and logical operations.
• It has a 16 bit flag register to reflect the results of execution by the ALU.
• The control system which is decoding section and timing and control unit decodes the op-codes and derives the necessary control signals to execute the instructions.
In short the functions of execution unit are
• To tell BIU where to fetch the instructions or data from.
• To decode the instructions.
• To execute the instructions.
Arithmetic Logic Unit (ALU):
Arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers.
General Purpose Registers of 8086
These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to have AX, BX, CX, and DX.
1. AX Register: AX register is also known as accumulator register that stores operands for arithmetic operation like divided, rotate.
2. BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction
Flag Registers of 8086:
Flag register in EU is of 16-bit long and is shown in fig below
Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. 8086 has 9 flags and they are divided into two categories: 1. Conditional Flags
2. Control Flags
Conditional Flags: -
Conditional flags represent result of last arithmetic or logical instruction executed.
Conditional flags are as follows:
• Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic.
• Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag; it is used internally by the processor to perform Binary to BCD conversion.
• Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity Flag is reset.
• Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
• Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set.
• Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of machine.
Control Flags: -
Control flags are set or reset intentionally to control the operations of the execution unit. Control flags are as follows:
1. Trap Flag (TP):
a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
c. When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled.
c. It can be set by executing instruction sit and can be cleared by executing CLI instruction.
3. Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to lower memory address.
c. When it is reset, the string bytes are accessed from lower memory address to higher memory address.
Base Pointer (BP):
Base Pointer is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI):
Source Index is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI):
Destination Index is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.
Segmentation and Segment Registers:
8086 Address Space
• The 8086 processor has a 20-bit physical address to directly address 1M byte of memory.
• Word size is only 16 bits.
• 20-bit address is splitted in 16-bit segment address and 16-bit offset address.
Segment address shifted four bits to the left and added to the offset value to generate a 20-bit effective address. Effective address is expressed as a 5 digit hex value (00000h to FFFFFh)
Memory Segments
• A segment is a block of 64Kb consecutive memory bytes.
• Segments are identified by segment numbers 0 - FFFFh.
• A 16 byte block makes up a paragraph.
• Segments always start on paragraph boundaries.
• Least significant nibble of segment address will always be 0.
Segment Registers
CS, DS, SS, and ES always point to low address end of segment.
CS - Code Segment register - points to a segment containing code.
DS - Data Segment register - points to a segment containing data.
SS - Stack Segment Register - points to a segment containing stack.
ES - Extra Segment register - points to a segment containing data Address.
Program memory –
Program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction.
Data memory –
The processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons (see "Data Memory" above).
Reserved locations:
• 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment: offset.
• FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address.
The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results of these operations can affect the condition flags. Different registers and their operations are listed below:
Addressing mode
Addressing mode indicated a way of locating data or operands.depending upon datatypes used in the instruction and the memory addressing mods,any instruction may belong to any of the addressing mode.
There are seven different types of 8086 microprocessore.
1. register addressing mode
2. immediate addressing mode
3. direct addressing mode
4. register indirect addressing mode
5. base relative addressing mode
6. base relative addressing mode
7. index addressing mode
1. Register addressing mode:
In this addressing mode the data will transfer to another register.all the register except IP(instruction pointer) may be used in this addressing mode.
2. Immediate addressing mode:
In this type of addressing mode the immediate data is the part of instruction.
Ex:- MOV BX,2567 H
3. Direct addressing mode:
In the direct addressing mode 16-bit memory location (offset address)is directly specified in the instruction itself.
4. Register indirect addressing mode:
in this addressing mode the offset address of data is in either BX,SI or DI register.the default segment is either DS or ES.
Ex:- MOV AX,[BX]
5. Base plus index addressing mode:
In this addressing mode the effective address of data is formed by adding contents of the contents of the base register (BX or BP) to the contents of an index register,(SI or DI)
Ex:- MOV CX,[BP][SI]
6. Register relative addressing mode:
In this addressing mode the data is available on effective address formed by adding an 8-bit or 16-bit displacement with the contents of the any one of register.
Ex:-MOV CX,[BX] 08H
7. Base relative index addressing mode:
The effective address is formed by adding an 8 or 16-bit displacement with the some of contents of any one of the base register or any one of index register.
EX:-MOV CX,[BX][SI]2678H
8. Index addressing mode:
In this addressing mode the offset address of data is stored into the memory location addressing by index register.
Data instruction set:-
1. Data transfer group:-
• MOV Rd , Rs:
This instruction transfers the contents of source to destination.we can load any register by immediate 8-bit as well as 16-bit data also.
MOV AX,2567 H
This instruction transfers the contents of specified register into the stack memory.whenever PUSH AX will be decremented by one. And then stored AH will transfer to the memory location pointed by the stack pointer.
Then again stack pointer will be decremented by 1 and the contents of AL will transfer to memory location pointed by stack pointer(sp-2)
This instruction when executed it loads the specified registers/memory with the contents of effective address formed by segment (stack segment)and stack pointer.
When this instruction is executd the contents of memory location pointed by SS:SP transferred to the lower bit of specifid register,stack pointer will incremented by one and the contents of memory location SS:SP transferred to the higher bit of specified register.
This instruction exchange the contents of the specified source and destination which may be register or one of them may be a memory location.
X CHG BX,[5000]
This instruction is used to read an input port.the address of part may be directly or indirectly given by register.the inputed data will be store in either AL on AX register.
Ex:-MOV DL,08
IM 03 H
This instruction is used for writing the data to the output port.the address of output port may be specified instruction directly or indirectly by register.
Ex:- OUT 08,AL
MOV DX,0008H
• LEA (load effective address):
The load effective address instruction load the effective address formed by destination operand into the specified source register.this instruction is more useful for ALP rather than machine language programming.
Ex:- LEA DX,address
LEA DX,add[SI]
This PUSHF(push flag into stack) instruction pushes the flag register into the stack memory.first the upper byte and then lower byte pushed on it.
The POP flag instruction loads the flag register completely (both bytes) from the stack memory locatin address by SS:SP
2. Arithimatic group:
• Add:
This instruction adds the contents of immediate data.memory location or register to the contents of another register or memory location.the results will stored in the destination operands.
Both the operands should not be immediate as well as from the memory location.
Ex:- Add AX,BX
ADD DX,2878H
ADD CX,[6000H]
ADD 0123H
• ADC:
This instruction performs the add operation between source and destination operands with carry and result stored into the destination operand.all the conditional flag affected by this instruction.
ADC DX,2878 H
ADC CX,[6000H]
ADC ,0123 H
• INC:
This instruction increments the contents of specified register by 1.all the comditional flags are affected except carry flag.
• DEC:
This instruction decrements the contents of specified register or memory location.all the conditional flags are affected except the carry flag.
DEC [5000]
• SUB:
This instruction subtract the contents of source operand from destination operand and the result is stored on the destination operand.source operand may be register,memory location or immediate data and the destination operand may be register.memory location.but source and destination both should not be memory location or immediate data.all conditional flags are affected by this instruction.
Ex:-SUB AX ,2376H
SUB CX,[5000]
SUB [6000],0256H
This instruction compares source operand (register,immediate data,memory location)with destination operand(which may be a register or memory location).for comparision it subtracts the source operand from destination operand but doesn’t change the content of any one.all the conditional flags are affected by this instruction.
CMP BX,1026H
CMP DX,[6000H]
This instruction multiplication the byte or word by the contents of AL.the unsigned byte or word may be in any one of the general purpose register or memory location.
The most significant word of the result is stored into DX register while the least significant word of the result is stored into AX.
All the conditional flags are affected by this instruction.

• IMUL(signed multiplication):
This instruction multiplies the signed byte in source operands by a signed in AL or signed word in source operand by a sign word in AX.the source can be GPR.memory location or index/base register.the higher word of result stored into DX register and lower word of result is stored into AX register.

• DIV(Unsigned division):
This instruction performs unsigned division .it divides an unsigned word or double word by a 16-bit or 8-bit operand.the dividend must be in AX register for 16-bit operation and division will be specified using any of the addressing mode except immediate addressing mode.and the result will be in AL()while AH will content the (remender).
If the result is two big to fit into AL type O interrupt is generated (divide by zero).
In case of double word the higher word should be in DX and the lower word should be in AX.
3.logical group:-
• AND:
This instruction bit-by+bit ANDs the source operands by destination operands and result will be in destination operand.
AND AX,[5000]
• OR:
This instruction performs the OR operation between source and destination operands
OR AX,[5000]
OR [6000],DX
• NOT:
This instruction complements the given operand.the operand may be from any register,memory location.
This instruction performs the X-OR operation bit-by-bit and the result stored into destination.
XOR CX,2617H
XOR [2000],DX
This instruction shifts the contents of specified register towards left and insert the zero into the newely introduced can sheft a word as well as a byte .it shifts one bit by default otherwise number of bits specified in the instruction.
Ex:-SHL AX,05H
This instruction shifts the contents of (byte or word)specified register towards right bydefaulty it will shift number of bits given by instruction itself.
This instruction shifts the contents of specified register towards right arithmeticly.if it is signed number then it will check MSB.if MSB is one the one will be placed at the newly introduced MSB.
Ex:- SAR BX,02H[BX=F27E]
1111 0010 0111 1110
1111 0010 0111 111
1111 0010 0111 11
• ROR(rotate right without carry):
This instruction rotates the contents of destination operand to the right(bitwise)either by 1 or number of bit specified by the instruction.
• ROL(rorate left without carry):
This instruction rotates the contents of destination operand to the left(birtwise)either by 1 nor number of bit specified by the instruction.
Ex:-ROL CX,06H
CF 0010 1010 1100 0011
O 1011 0000 1100 1010
• RCR(rotates right through carry):
This instruction rotates the contents of destination operand through carry(bitwise) by either 1 or number of bits specified by instruction.
Here LSB will transfer to carry flag and carry flag will transfer to MSB.
Ex:-RCR CX,06H
0010 1010 1100 0011
0001 1100 1010 1011
• RCL(rotate light through carry):
This instruction rotates the destination operand to left through carry (bitwise)by either or number of bits specified by instruction.
Ex:-RCL CX,06H
0010 1010 1100 0011
1011 0000 1110 0101
• REP(repeat instruction prifix):
This instruction repeats the instruction to which it is prefix to which it is prefix after each iteration the bydefault counter cx will be decremented or incremented by one or two (if word decremented by two and byte decremented by one).
This instruction transfers the byte or word (string) from DS:SI memory location to ES:DI memory location.
MOV AX,4000H
MOV AX,8000H
MOV AX,1000H
CLD(clear direction flag)
MOV CX,0005H
• CMPS(comparing two string):
This instruction compairs two string of byte or word.the length of the string must be stored into CX register.if both the byte or word are equal the zero flag is set otherwise reset.
The DS:SI and ES:DI points the two string.
MOV AX,4000
MOV AX,8000
MOV DI,1000H
MOV CX,0005H
If string are equal then CX=0 and Z=1
Otherwise Z=0
• SCAS(scan string):
This instruction scans a string of bytes or word for an operand byte or word specified in the AL or AX register .the length of the string is stored in CX register is pointed by ES:DI
MOV AX,4000
MOV DI,1000H
MOV CX,0005H
If the maching of word found then zero will be set otherwise reset.
• LODS(load string):
The lods instruction loads AL or AX register by the contents of a string pointed by DS:SI.the SI is modified according to direction flag(DF).
• STOS(store string):
The STOS instruction stores the contents of a AL?AX register to a memory location of string pointed by ES:DI
5. Branch instruction (control transfer):
The control transfer instruction transfer the flow of execution of the program to a new address specified in the instruction directly or indirectly.when this type of instruction is executed and CS and IP get loaded by new value of CS and IP
There are two types of branching instruction:-
1.unconditional branching
2.conditional branching instruction
a) unconditional branching instruction:
in this type of instruction the execution control is transferred to the specified location independent of any status or condition.
b) conditional branching instruction:
in this type of instruction,the control is transferred to the specified location,after satisfy the particular condition,otherwise the execution continue in normal flow sequence.
a) unconditional branching instruction:
This instruction is used to call a subroutine from a main program.the address of subroutine may be specified directly or indirectly.there are again two types of subroutine depending upon whether it is available in same segment.(NEAR CALL) or in another segment (far CALL).
On execution of this instruction,it stores the incremented IP and CS into the stack memory and loads the CS and IP with the subroutine to be called repectively.
In case of near CALL ,it pushes only IP register and in case of far CALL it pushes IP as well as CS
• RET(return):
at each CALL instruction the IP and CS of next instruction is pushed on the stack memory before the control is transferred to the subroutine the RET instruction must be executed.
When it is executed the previous stored contents of IP and CS along
with flag are retrived into the CS and IP
the subroutine may be far or case of near subroutine only IP will be retrived,otherwise CS and IP both will be retrived.
• JMP(unconditional jump):
this instruction unconditionally transfer the control to the specified address using 8-bit or 16-bit displacement no flags are affected by this instruction.
this instruction executed the part of program from the lable or address specified by the instruction itself upto the loop instruction .this will execute repeatedly until the counter become zero.
Ex: MOV AX,2567 H
MOV CX,0005H
INT 21H • In the interrupt structure of 8086,256 intreeupt are defined corresponding to the types from 00-FFH.when an INT instruction
Is executed the type byte N is multiplied by 4 and the contents of IP and CS of the interrupt service routine will be taken from the hexadecimal multiplication as offset address and 0000 as segment address.for the execution of this instruction IF (interrupt flag) must be set.
• IRET(interrupt return):
When an interrupt service routine is to be called before transferring control to it,the IP,cs and flag register are stored on the stack memory to indicate the location from where the execution is to be continued after the ISR is executed.
At the end of each ISR when IRET is executed the value of IP,CS and flags are retrived from the stack to continue the execution of main program.
b) conditional branching instruction:
• JZ/JE (jump if zero flag is 1)
• JNZ/JNE(jump if ZF=0)
• JS (jump if SF=1)
• JNS (jump if SF=0)
• JO (jump if OF=1)
• JNO (jump if OF=0)
• JP (jump if PF =1)
• JNP (jump if PF =0)
• JB/JC (jump if CF=0)
• JNB/JNC (jump if CF=0)
• JBE (jump if ZF=1 or CF=1)
• JLE (jump if ZF=1 OR CF=0)
• JL (Jump if CF=0)
• JNL (jump if CF=1)
• JNBE (jump if CF=0 or ZF=0)
• JNLEW (jump if CF=1 or ZF=0)
Flag manipulation:
• CLC (clear carry)
• CMC (Complement carry)
• STC (set carry)
• CLD ( clear direction flag)
• STD (set direction flag)
• CLI (clear instruction flag)
• STI (set instruction flag)
Machine control instruction:
Memory segmentation:
Te memory in 8086 up based system is organized as segmented this scheme the complete physical memory may be divided into a number of logical segment.each segment is 64kb in size and is addressed by one of the segment register.
The sixteen bit content of the segment register actually point to the statrtiog location of a particular address a specific memory location within a segment we need an offset address.the off-set address is also 16-bit long so that the physical address formed 20-bit long by using segment atarting address and offset address.
Suppose,CS=2000H and offset=1000H
CS X 10 =20000
+OFFSET =1000
Physical addresss =21000H
The total 1 MB memory can be access by 1 HP 8086 and each segment is of 64 kb long. Hence the total number are available.
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